Tuesday, November 13, 2007

Guide to Operation System Part 3

The Von Neumann Architecture
It has a fixed set of electronic parts which can be manipulated to perform various tasks determined by a variable program.

It consists of:
- A central processing unit ( CPU )
- A primary memory unit
- A collection of I/O devices
- Buses to interconnect the components

Central Processing Unit
- ALU: it is Responsible for performing arithmetic and logical operations

- Control Unit: it causes a sequence of instructions stored in memory to be retrieved and executed.

CU comprises
- Fetch Unit: Fetches an instruction from memory- Decode Unit: Decode an instruction
- Execute Unit: Signal ALU to execute instruction
- Instruction Register (IR): Contains a copy of current instruction
- Program Counter Register (PC): Contains the memory address of the next instruction the unit is to load

Note: It works on fetch-execute cycle

Primary Memory Unit (RAM)
it consists of 3 registers in order to interact with the CPU.

- Memory Address Register(MAR): stores address of data to be read from or written to
- Memory Data Register(MDR): stores data that is read or to be written
- Command Register(CMD): stores the command to be executed

Device Controller Interface
It includes the following as part of the interface:
- Data Register
- Command Registers
- Status flags with includes Done, Busy and Error Code

Two ways CPU initiate I/O
- Polling
Simplest way for CPU keeps polling the device to see the state of the I/O. If I/O not done then CPU executes a busy-wait command to wait for the I/O to end.
Note: this method will waste precious processor cycle

- Interrupt
A more complicated way is to have CPU implement an interrupt request flag. When I/O is done interrupt request flag is set to signal the end of I/O.
The Interrupt handler usually needs to perform a Context Switch to save the state of CPU at the time, so that it can be reused later.

Direct Memory Access (DMA)
Transfer data to and from primary memory address without CPU intervention.

It relieves CPU of data transfer operation. CPU can start a DMA block transfer and then perform other work in parallel with DMA operation. This significantly increase machine I/O performance and increase CPU throughout.

Posted by Zack at 11:26 PM